9724088458
Hello! I’m Meghana
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I’m thrilled you’re here. Please take a moment to explore my site, where you’ll find details on my background, experience, skills and more. To learn more or connect on an opportunity, don’t hesitate to reach out.
Bio
From a young age, I’ve always had a sense of motivation and passion driving me forward. Whether it’s exploring unique opportunities, learning additional skills, or meeting new people, I bring these values to every experience throughout my life on a personal and professional level. I do have a passion to explore out of box approaches. To learn more about me, keep exploring my site or reach out directly.
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Education
What I’ve Learned
September 2011Â - June 2015
UNDERGRADUATE
Visvesvaraya Technological University GPA 4/4
August 2015 - August 2017
GRADUATE
University of Texas at Dallas GPA 3.8/4
My Experience
Background & Expertise
May 2016 - Dec 2016
Graduate technical Intern in SOC team
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• SV Assertions: Concurrent and Immediate Assertions for clock gates, Assertions for Advanced Demod module.
• Python: Automated to generate procedural diagrams, which helped the whole team to debug error in Level 1 tests.
• Perl: Automating the work by scripting for memory path delay updation and to run all regression test cases in parallel.
• Error tracing and debugging :Running existing regression lists and debugging errors using Verdi and DVE
• Test cases : Update/develop tests to verify access to memories,
• Regression Runs at LTE TOP level – Full Regression Suite, Power Aware Regression runs
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May 2017 - May 2018
Graphics Hardware Engineer
RTL Integration: Changing few files to adopt to SOC environment, running standalone test with upf / without upf/ with
checkers trackers, resolving functional issues , syntax issues and delivering it to SOC
• Verification of L1 test list: Coded basic level test cases using System Verilog.
• MODEL BUILD: resolving connectivity issues, adding new units/clusters, modifying new features in IP level by unit
owner’s support and delivering the new model by resolving tracker checker issues and inserting repeaters.
• IP Drop Score: Evaluated the drop score, analysis of failing rules and giving expected drop score.
June 2018 - June 2022
SOC Design Verification Engineer
• Constrained Random Test development using SV: Development of test from scratch to cover new feature, new design
changes and to cover new bugs from post silicon (Recognized to cover a significant bug)
• Test extension using OVM sequences: The sequences from IP are extended in SOC and drivers are overwritten to drive
the design. Utilization of register model to code sequences
• Verification owner for Ring Oscillators and PLL at SOC and found significant bugs on RTL (Recognized by department
for it)
• Assertion and coverage : Coded power gate assertions covering all corner cases and enabled spyglass Jasper Gold tool
for it to find bugs in initial phase of project
• Innovation: Introduced part compile into SOC. Automated few legacy power gating test cases to generate for every
project
• Debug: Debugging legacy and new tests for new projects using Verdi/ DVE.
• Leadership: Managing power ownership and guiding five contract workers. Mentored an intern.
• 3 Recognitions for the excellent work
My Skills and Certifications
Verification using UVM and system verilog
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UVM testbench development
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Perl Scripting
Let’s Connect
I’d love to hear from you.
Home Address - 755 E capitol avenue, Apt J211, Milpitas - 95035
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Office Address - 2100 Logic Dr, San Jose, CA 95124
9724088458